25 research outputs found

    LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

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    The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

    A VGA linearity improvement technique for ECG analog front-end in 65nm CMOS

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    This paper presents a 65nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5-100mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loopgain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25-50dB gain, and post-layout simulations showed a 15dB reduction in the harmonic distortion for 20mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108μm2 silicon area and consumes 0.43μA from a 1.2V power supply

    A positive feedback-based op-amp gain enhancement technique for high precision applications

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    A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage, and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gainboosting technique. The proposed opamp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1V supply. The circuit draws a total static current of 295μA and occupies 5000μm2 of silicon area

    A high sensitivity and low power circuit for the measurement of abnormal blood cell levels

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    This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply

    A high value, linear and tunable CMOS pseudo resistor for bio-medical applications

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    A sub-threshold MOS based pseudo resistor featuring a very high value and ultra-low distortion is proposed. A band-pass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The stand-alone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a lowpass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature

    An OTA gain enhancement technique for low power biomedical applications

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    The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area

    Simulation of driver fatigue monitoring via blink rate detection, using 65nm CMOS technology

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    This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply

    A CMOS blood cancer detection sensor based on frequency deviation detection

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    This paper proposes a technique to detect Leukaemia (blood cancer) based on the frequency modulation of a relaxation oscillator by changes in the dielectric constant of blood cells. A novel 16-bit frequency detector with a digital output has been proposed to detect the frequency difference between two oscillators based on healthy blood and Leukaemic blood. A circuit has been designed, to operate on a 1.2V supply, post layout simulations shows 0.35mA current consumption. The chip Area including pads~0.6mm∗0.45m

    A 0.6V MOS-only voltage reference for bio-medical applications with 40ppm/0c temperature drift

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    This paper exploits the CMOS beta multiplier circuit to synthesize a temperature independent voltage reference suitable for low voltage and ultra-low power bio-medical applications. The technique presented here uses only MOS transistors to generate PTAT and CTAT currents. A selfbiasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm, and at room temperature it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from -40 to 1250C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/0C

    A 0.55V Bandgap reference with a 59ppm/0c Temperature coefficient

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    This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with existing BJT-based reference circuits, by using a MOS transistor operating in subthreshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55V, and generates a 286mV reference voltage with a temperature coefficient of 59ppm/°C. The circuit takes 413nA current from 0.55V supply and occupies 0.00986mm2 of active are
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